A typical computer includes a processor and memory. Frequently a memory controller is coupled between the processor and the memory. One function of the memory controller is to oversee the movement of data into and out of the memory.
FIG. 1 is a block diagram of a memory controller 20 coupled to memory in a typical computer. The memory is installed in a plurality of memory slots 10-13. Memory slots 10-13 support memory devices such as dynamic random access memory ("DRAM") devices that are packaged as single in-line memory modules ("SIMMS") and dual in-line memory modules ("DIMMS").
Memory controller 20 in FIG. 1 includes a memory address bus 22 for addressing each memory device. Memory address bus 22 is a multiple bit bus, and each bit typically requires a memory address pin on memory controller 20.
Increasing the number of memory devices in the computer increases the load on memory address bus 22. When the number of memory devices exceed a fixed amount, the resulting load prevents memory address bus 22 from functioning properly. Therefore, when the fixed amount is exceeded, memory address bus 22 cannot be directly coupled to the memory devices in memory slots 10-13.
One known method for reducing the load on memory address bus 22 when the number of memory devices are increased is shown in FIG. 1. Memory address bus 22 is first input to buffers 30, 40. Buffers 30, 40 are then coupled respectively to memory slot 10-11 and 12-13. As shown, buffer 30 is coupled to memory slot 10 via line 32 and memory slot 11 via line 34. Similarly, buffer 40 is coupled to memory slot 12 via line 42 and memory slot 13 via line 44. The buffers reduce the load on memory address bus 22.
However, adding buffers 30, 40 to the computer increases the cost of the computer. Further, buffers 30, 40 decrease the performance of the computer because they add a time delay between memory controller 20 and the memory modules inserted in slots 10-13. Therefore, it is desirable to eliminate buffers 30, 40.
One way to eliminate buffers 30, 40 and still reduce the load on memory address bus 22 is to add an additional memory address bus to memory controller 20. Each memory address bus therefore has only half of the load imposed on it by the memory devices in memory slots 10-13. However, this requires the number of memory address pins on memory controller 20 to be doubled.
Further, integrated circuits such as memory controller typically have a maximum ratio of input/output ("I/O") pins to each power and ground pin. When the ratio is increased, the I/O signals are subjected to increased ground bounce and increased simultaneous switching output induced delay which are detrimental to a computer. If the ratio exceeds the maximum, the computer that includes the integrated circuit may not be operable. For a typical memory controller coupled to DRAMs, the maximum ratio of memory address bus pins to each power and ground pin can be approximately 4:1. Therefore, for every four memory address pins on bus 22, memory controller 20 requires one power pin and one ground pin.
Because of the maximum ratio, if the number of memory address bus pins on memory controller 20 is doubled as described above, the number of required power and ground pins also increases. However, it is desirable to minimize the number of pins on memory controller 20 because as the number of pins increase, the corresponding number of pads on the memory controller's die must also be increased. This requires the size of the die itself to also be increased, which greatly increases the cost of memory controller 20. Based on the foregoing, there is a need for a memory controller that is not required to be coupled to buffers, and that has a minimal number of pins.